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RM0008
Figure 11. Clock tree
Connectivity line devices: reset and clock control (RCC)
40 kHz
L S I
RC
to independent w a tchdog
IWDGCLK
O S C 3 2_IN
O S C 3 2_OUT
3 2.76 8 kHz
L S E
O S C
L S I
to RTC
L S E
RTCCLK
/12 8
RTC S EL[1:0]
C SS
H S E
to Fl as h prog. IF
FLITFCLK
XT1 to MCO
8 MHz
H S I RC
PLLMUL
H S I
S Y S CLK
s y s tem clock
O S C_IN
3 -25 MHz
/2
x4, x5,... x9, PLLCLK
O S C_OUT
H S E
O S C
/1,2, 3 ....
..../15, /16
x6.5
PLLVCO
S W
PREDIV1
PREDIV1 S CR
PLL S CR
U S B pre s c a ler
/2, 3
OTGF S CLK
PLL2MUL
4 8 MHz
to U S B OTG F S
x 8 , x9,... x14,
x16, x20
PREDIV2
to I2 S 2 interf a ce
/1,2, 3 ....
..../15, /16
PLL 3 MUL PLL2CLK
to MCO
PLL 3 VCO
x 8 , x9,... x14,
to I2 S3 interf a ce
x16, x20
PLL 3 CLK to MCO
MCO[ 3 :0]
HCLK to AHB bus , core memory a nd DMA
H S E
H S I
/2
to Cortex S y s tem timer
MCO
PLLCLK/2
FCLK Cortex free r u nning clock
PLL2CLK
PLL 3 CLK/2
PLL 3 CLK
XT1
S Y S CLK
72 MHz m a x.
( s ee note1)
AHB pre s c a ler
/1,/2 ../512
APB1 pre s c a ler
/1, 2, 4, 8 , 16
APB2 pre s c a ler
/1, 2, 4, 8 , 16
3 6 MHz m a x
Peripher a l clock en ab le
TIM2, 3 ,4,5,6,7
If(APB1 pre s c a ler =1) x1
el s e x2
Peripher a l clock en ab le
72 MHz m a x
Peripher a l clock en ab le
PCLK1
to APB1 peripher a l s
to TIM2, 3 ,4,5,
6&7
TIMxCLK
PCLK2
to APB2 peripher a l s
Ethernet
PHY
TIM1
If(APB2 pre s c a ler =1) x1
el s e x2
to TIM1
TIMxCLK
ETH_MII_TX_CLK
MACTXCLK
Peripher a l clock en ab le
ETH_MII_RX_CLK
/2, /20
MII_RMII_ S EL
in AFIO_MAPR
MACRXCLK
to Ethernet MAC
ADC pre s c a ler
/2, 4, 6, 8
ADCCLK
14 MHz m a x
to ADC1,2
MACRMIICLK
a i15699c
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.
The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the
application in the choice of the external crystal or oscillator to run the core and peripherals
at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB
OTG FS.
A single 25 MHz crystal can clock the entire system and all peripherals including the
Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance,
an audio crystal can be used. In this case, the I2S master clock can generate all standard
sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.
For more details about clock configuration for applications requiring Ethernet, USB OTG FS
and/or I 2 S (audio), please refer to "Appendix A Applicative block diagrams" in your
connectivity line device datasheet.
Doc ID 13902 Rev 9
107/995
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